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Chapter 5
Module Design
This chapter provides information about the functionality and design details of the various
modules that constitute the MPC8272ADS.
5.1
Reset and Reset Configuration
The following are reset sources on the MPC8272ADS:
• Power-on reset
• Manual hard reset
• Manual soft reset
• PCI bus reset
• MPC8272 internal sources. For more information, see the MPC8272 PowerQUICC
II
Family Reference Manual.
TM
5.1.1
Power-On Reset
The power-on reset to the MPC8272 initializes the processor state after power-on. A
dedicated logic using Seiko S-80728AN-DR-T1, which is a voltage detector of 2.8V +/-
2.4%, assert
PORESET input to the PowerQUICC II for a period of ~2.5sec. This time
s
period is sufficient to cover the V
regulator. It is assumed that the stabilization time for both linear regulators (see Section 7.1,
"Power Supply") are about the same. Furthermore, power-on reset may be generated
manually by an on-board dedicated push-button (SW1). Power-on reset can also be
generated by the JTAG logic, which is integrated with BCSR.
5.1.2
Power-On Reset Configuration
At the end of Power - On reset sequence, MODCK(1:3) are sampled by the MPC8272 to
configure the various clock modes of the MPC8272 (core, cpm, bus, PCI...). Selection
between the MODCK(1:3) combination options is done by means of dip-switches on the
mother board while PCI_MODCKH(0:3) are obtained from the relevant dedicated
dip-switches.
stabilization also, powered by a different voltage
DDL
Chapter 5. Module Design
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