Reset Programming Model; Reset Configuration Word Low Register (Rcwlr) - Freescale Semiconductor MSC8144E Reference Manual

5.3 Reset Programming Model

This section describes the following reset registers in detail:
Reset Configuration Word Low Register (RCWLR), page 5-17.
Reset Configuration Word High Register (RCWHR), page 5-19.
Reset Status Register (RSR), page 5-21.
Reset Protection Register (RPR), page 5-23.
Reset Control Register (RCR), page 5-24.
Reset Control Enable Register (RCER), page 5-25.
Note: The Reset register base address is 0xFFF24800.

5.3.1 Reset Configuration Word Low Register (RCWLR)

RCWLR
Bit 31 30 29
CLKO
Type
Reset 0 0 0
Bit 15 14 13
Type
Reset 0 0 0
The RCWLR is a read-only register set according to the reset configuration word low loaded
during the reset flow. Table 5-8 defines the RCWLR bit fields.
Name Reset
CLKO 0 CLKOUT Source
31–30 This field selects the source for CLKOUT. See
Chapter 7, Clocks for source clock definitions.
— 0 Reserved. Write to zero for future compatibility.
29–26
SF 0 SerDes Filter
25 Selects the SerDes filter.
— 0 Reserved. Write to zero for future compatibility.
24
RV 0 RapidIO V
23
Freescale Semiconductor
Reset Configuration Word Low Register
28 27 26 25
— SF
0 0 0 0
12 11 10 9
SPCI SDDR SM3 —
0 0 0 0
Table 5-8. RCWLR Bit Descriptions
Description
Select
DD
MSC8144E Reference Manual, Rev. 3
24 23 22 21
— RV SCLK
R
0 0 0 0
8 7 6 5
GPD CPD SPD
R
0 0 0 0
00 Source is Clock2.
01 Source is Clock9.
10 Source is Clock10.
11 CLKOUT is always low.
0 200 ppm SerDes digital filter bandwidth
1 600 ppm SerDes digital filter bandwidth
0 1 V
1 1.2 V
Reset Programming Model
Offset 0x00
20 19 18 17
RIOE 1x SGMII1 SGMII2
0 0 0 0
4 3 2 1
MODCK
0 0 0 0
Settings
16
0
0
0
5-17