Soft Reset Sequence; Reset Status Register (Rsr) - Freescale Semiconductor MPC850 User Manual

11.1.9 Soft Reset Sequence

Figure 11-2 shows the reset sequence following an internal or external soft reset event.
Internal or external
SRESET asserted
16 clocks expire
& DSCK high
Debug
Mode
•
DSDI is sampled to determine
clocked or self-clocked mode

11.2 Reset Status Register (RSR)

The 32-bit reset status register (RSR) is powered by the keep alive power supply. It is
memory-mapped into the MPC850 system interface unit register map and receives its
default reset values at power-on reset.
Bit 0 1 2
Field EHRS ESRS LLRS SWRS CSRS DBHRS DBSRS JTRS
Reset
R/W
Bit 16 17 18
Field
reset
r/w
The RSR bits are described in Table 11-2 Note that the bits in this register (except those that
are reserved) are cleared by writing ones; writing zeros has no effect.
•
Internal initiated SRESET assert
•
SRESET
The time counter is set to 512
Timer expires (after 512 clocks)
•
Sample debug port configuration from DSDI and DSCK pins
•
Wait Negate SRESET
•
Wait for 16 clocks
External SRESET still asserted
16 clocks expire
Test for
& DSCK low
HRESET or
SRESET
Start normal execution
(From system reset interrupt exception vector) (From system reset interrupt exception vector)
Figure 11-2. Soft Reset Sequence
3 4 5
1100_0000_0000_0000
19 20 21
0000_0000_0000_0000
Figure 11-3. Reset Status Register (RSR)
Chapter 11. Reset
Reset Status Register (RSR)
6 7 8 9
R/W
22 23 24 25
—
R/W
10 11 12 13 14
—
26 27 28 29 30
15
31