Motorola PowerQUICC II MPC8280 Series Reference Manual page 381

31
Field
Reset
R/W
Addr
15
Field BA
Reset
R/W
Addr
Figure 9-46. General Purpose Local Access Base Address Registers (GPLABARx)
Table 9-33 describes GPLABARx fields.
Bits Name
31–12 Base address
11–4
3 Prefetchable
2–1 Type
0 Memory space indicator Address is mapped to memory space (hardwired to 0).
9.11.2.15 Subsystem Vendor ID Register
Figure 9-47 and Table 9-34 describe the subsystem vendor ID register.
15
Field
Reset
R/W
Addr
MOTOROLA
Freescale Semiconductor, Inc.
0000_0000_0000_0000
0x16 (GPLABAR0); 0x1A (GPLABAR1)
12 11
0000_0000_0000_0000
0x14 (GPLABAR0); 0x18 (GPLABAR1)
Table 9-33. GPLABARx Field Descriptions
Represents the base address for the inbound GPLA memory window. The number
of upper bits that the PCI bridge allows to be writable is selected through the PICMR;
see Section 9.11.1.17, "PCI Inbound Comparison Mask Registers (PICMRx)."
Hardwired to zeros. (The minimum window size allowed is 4K.)
Corresponds to the prefetchable bit in the PICMR; see Section 9.11.1.17, "PCI
Inbound Comparison Mask Registers (PICMRx)."
Hardwired to 00 to indicate that the address can be located anywhere in 32-bit
address space.
0000_0000_0000_0000
Figure 9-47. Subsystem Vendor ID Register
Chapter 9. PCI Bridge
For More Information On This Product,
Go to: www.freescale.com
BA
R/W
4
BA
R/W
Description
SVID
R/W
0x2C
Configuration Registers
16
3 2 1 0
PRE T MSI
0
9-59