Register Description Of Flash Memory; 17.23.1 Programming/Erasing Interface Register - Renesas H8S/2319 series Hardware Manual

Table 17-49 Register/Parameter and Target Mode
Programming/ FCCS
erasing interface
FPCS
registers
PECS
FKEY
FMATS
Programming/ FPFR
erasing interface
FPEFEQ
parameter
FMPAR
FMPDR
FEBS
RAM emulation RAMER
Notes: 1. The setting is required when programming or erasing user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target MAT.
17.23

Register Description of Flash Memory

17.23.1 Programming/Erasing Interface Register

The programming/erasing interface registers are as described below. They are all 8-bit registers
that can be accessed in byte. Except for the FLER bit in FCCS, these registers are initialized at a
power-on reset, in hardware standby mode, or in software standby mode. The FLER bit is not
initialized in software standby mode.
(1) Flash Code Control and Status Register (FCCS)
FCCS is configured by bits which request the error occurrence during programming or erasing
flash memory and the download of on-chip program.
Bit : 7
—
Initial value : 1
R/W : R
Bit 7—Reserved: This bit is always read as 1. The write value should always be 1.
Initiali-
Download zation
—
—
—
—
— —
—
— —
— —
— —
— —
6 5
— — FLER
0 0
R R
Program-
ming Erasure
— —
— —
— —
1 1
* *
— —
—
—
—
— —
4 3
— —
0 0
R R R
Rev. 5.00, 12/03, page 675 of 1088
RAM
Read Emulation
— —
— —
— —
— —
2
*
—
— —
— —
— —
— —
— —
—
2 1 0
— SCO
0 0 0
R (R)/W