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Section 20 LPC Interface (LPC)
Bit
Bit Name Initial Value Slave Host Description
1
SMIE4
0
0
0
20.3.16 SERIRQ Control Register 3 (SIRQCR3)
SIRQCR3 contains bits that select the host interrupt request outputs.
Initial
Value
Bit
Bit Name
7
SELIRQ15
0
6
SELIRQ14
0
5
SELIRQ13
0
4
SELIRQ8
0
3
SELIRQ7
0
2
SELIRQ5
0
1
SELIRQ4
0
0
SELIRQ3
0
Rev. 1.00 Apr. 28, 2008 Page 656 of 994
REJ09B0452-0100
R/W
R/W
Host SMI Interrupt Enable 4
Enables or disables an SMI interrupt request when
OBF4 is set by an ODR4 write.
0: Host SMI interrupt request by OBF4 and SMIE4
is disabled
[Clearing conditions]
•
Writing 0 to SMIE4
•
LPC hardware reset, LPC software reset
•
Clearing OBF4 to 0 (when IEDIR4 = 0)
1: [When IEDIR4 = 0]
Host SMI interrupt request by setting OBF4 to 1
is enabled
[When IEDIR4 = 1]
Host SMI interrupt is requested
[Setting condition]
Writing 1 after reading SMIE4 = 0
R/W
Reserved
The initial value should not be changed.
R/W
Slave Host Description
R/W
Host IRQ Interrupt Select
R/W
These bits select the state of the output on the
SERIRQ pins.
R/W
0: SERIRQ pin output is in the Hi-Z state
R/W
1: SERIRQ pin output is low
R/W
R/W
R/W
R/W
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