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Initialization Sequence
Bits
Name
7
RCTL[0]
8:31
---
14.8.8
FEC Transmit FSM Register—MBAR + 0x31C8
The transmit finite state machine register (XMIT_FSM) controls operation of appending CRC. Typical use is enabled and CRC is appended.
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:5
—
6
XFSM[1]
7
XFSM[0]
8:31
---
14.9
Initialization Sequence
This section describes which registers are hardware reset, which are reset by the FEC and what locations the user must initialize prior to
enabling the FEC.
14.9.1
Hardware Controlled Initialization
Some registers in the FEC are reset by internal logic. Specifically those registers are control logic that generate interrupts, cause outputs to be
asserted and, in general, configuration control bits.
Other registers are reset when the ETHER_EN bit is not asserted (i.e., cleared). To halt operation ETHER_EN is deasserted by either a hard
reset or by software. By deasserting ETHER_EN configuration control registers such as X_CNTRL and R_CNTRL are not reset, but the entire
data path is reset.
Table 14-40
shows the effect deasserting ETHER_EN has on Ethernet MAC operation and registers.
Register/Machine
RECV block
14-34
0 = Disable fec_enable as a reset to FIFO controllers.
1 = Enable fec_enable as a reset to FIFO controllers.
Reserved
Table 14-39. FEC Transmit FSM Register
2
3
4
5
6
Reserved
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Reserved
0 = Do not append CRC.
1 = Append CRC (typical use).
0 = Disable CRC FSM.
1 = Enable CRC FSM (typical use is enabled).
Reserved
Table 14-40. ETHER_EN De-Assertion Affect on FEC
XMIT block
Tx/Rx FIFO
MPC5200B Users Guide, Rev. 1
Table 1-1.
Description
7
8
9
10
0
0
0
0
23
24
25
26
Reserved
0
0
0
0
Description
Transmission Aborted (bad CRC appended)
Receive activity aborted
Reset control logic dependent on reset_cntrl
11
12
13
14
Reserved
0
0
0
0
27
28
29
30
0
0
0
0
Reset Value
Freescale Semiconductor
15
0
31 lsb
0
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