Table of Contents
Advertisement
19.4.17 Descriptor Group Upper Address Register (GAUR)
GAUR contains the upper 32 bits of the 64-bit hash table used in the address recognition process for
receive frames with a multicast address. You must initialize this register.
Address: 0xFC03_0120
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 19-17. Descriptor Group Upper Address Register (GAUR)
Field
31–0
The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for
GADDR1
receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains
hash index bit 32.
19.4.18 Descriptor Group Lower Address Register (GALR)
GALR contains the lower 32 bits of the 64-bit hash table used in the address recognition process for
receive frames with a multicast address. You must initialize this register.
Address: 0xFC03_0124
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 19-18. Descriptor Group Lower Address Register (GALR)
Field
31–0
The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for
GADDR2
receive frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains
hash index bit 0.
19.4.19 Transmit FIFO Watermark Register (TFWR)
The TFWR controls the amount of data required in the transmit FIFO before transmission of a frame can
begin. This allows you to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
latency (TFWR = 11) due to contention for the system bus. Setting the watermark to a high value
minimizes the risk of transmit FIFO underrun due to contention for the system bus. The byte counts
associated with the TFWR field may need to be modified to match a given system requirement (worst case
bus access latency by the transmit data DMA channel).
Freescale Semiconductor
GADDR1
Table 19-21. GAUR Field Descriptions
Description
GADDR2
Table 19-22. GALR Field Descriptions
Description
MCF5329 Reference Manual, Rev 3
Fast Ethernet Controller (FEC)
Access: User read/write
8
7
6
5
4
3
2
1
0
Access: User read/write
8
7
6
5
4
3
2
1
0
19-21
Advertisement
Table of Contents
