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TDM Interface
Table 19-10. Received Data Delay for Receive Frame Sync
Frame Sync Delay
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
Note:
Receive clocks is the number of receive clocks between the sample of the receive frame sync and the sample of first
data bit of the received frame.
19.7.1.3 TDMx Transmit Interface Register (TDMxTIR)
TDMxTIR
Bit
31
30
29
Type
Reset
0
0
0
Boot
0
0
0
15
14
13
TFTL
TSTL
TSO
Type
Reset
0
0
0
Boot
0
0
0
TDMxTIR defines the TDM x transmitter interface operation.
Name
Reset
—
0
Reserved. Write to zero for future compatibility.
31–17
TBOR
1
Transmit Byte Order
16
Indicates how to transmit data residing in the transmit
external memory buffer. The boot program writes a 1 to
this bit.
TFTL
0
Transmit First Threshold Level
15
Determines whether the Transmit first threshold
interrupt is pulse or level. For details, see Section
19.2.6.3.
19-46
Frame Sync Edge
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TDMx Transmit Interface Register
28
27
26
25
0
0
0
0
0
0
0
0
12
11
10
9
TAO
SOL
SOE
0
0
0
0
0
0
0
0
Table 19-11. TDMxTIR Bit Descriptions
Description
MSC8144E Reference Manual, Rev. 3
Data Edge
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
24
23
22
21
—
R/W
0
0
0
0
0
0
0
0
8
7
6
5
—
TFSD
R/W
0
0
0
0
0
0
0
0
0
Transmit high address first.
1
Transmit low address first.
0
Transmit first threshold interrupt is pulse.
1
Transmit first threshold interrupt is level.
Receive Clocks
0.0
0.5
0.5
0.0
1.0
1.5
1.5
1.0
2.0
2.5
2.5
2.0
3.0
3.5
3.5
3.0
Offset 0x3FE8
20
19
18
17
TBOR
0
0
0
0
0
0
0
0
4
3
2
1
TSL
TDE
TFSE TRDO
0
0
0
0
0
0
0
0
Settings
Freescale Semiconductor
1
16
1
1
0
0
0
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