Dma Channel Enable Register (Dmacher) - Freescale Semiconductor MSC8144E Reference Manual

Direct Memory Access (DMA) Controller

14.6.3 DMA Channel Enable Register (DMACHER)

DMACHER
Bit 31 30 29
Type
Reset 0 0 0
Bit 15 14 13
EN15 EN14 EN13 EN12 EN11 EN10
Type
Reset 0 0 0
Each bit in DMACHER corresponds to DMACHCRx[ACTV]. When an ENx bit is set, it
activates channel x. When ENx bit is reset, it does not affect the channel. DMACHER is cleared
at reset, and the user enables a channel request by setting the appropriate bit. The register allows
simultaneous activation of channels after they are configured. While channel x is disabled, all
requests are ignored and any non-serviced request is lost. The DMA controller logic resets the
ENx bit when the channel task completes.
14.6.4 DMA Channel Disable Register (DMACHDR)
DMACHDR
Bit 31 30 29
Type
Reset 0 0 0
Bit 15 14 13
DIS15DIS14 DIS13 DIS12 DIS11 DIS10
Type
Reset 0 0 0
Each bit in the DMACHDR corresponds to a channel. Writing a 1 to DISx disables channel x.
Writing a 0 to DISx does not affect the channel. DMACHDR is cleared at reset. The register
allows simultaneous deactivation of channels during normal operation. While channel x is
disabled, all requests are ignored and any non-serviced request is lost. The DISx bit is reset by the
DMA logic.
When the user writes either a 1 to DMACHDR[DISx] or a 0 to DMACHCRx[ACTV], the
channel is shut down. If more channel requests are pending on the bus interface, the channel is
not disabled. The DMACHDR[DISx] and corresponding DMACHER[ENx] and
CHCRx[ACTV] are all set until the pending channel transactions are closed. When all
transactions are closed, the DMA logic resets the DMACHER[ENx] and DMACHCRx[ACTV]
bits. After the channel is disabled, you must poll DMACHASTR to acknowledge that the channel
14-28
DMA Channel Enable Register
28 27 26 25
0 0 0 0
12 11 10 9
EN9
0 0 0 0
DMA Channel Disable Register
28 27 26 25
0 0 0 0
12 11 10 9
DIS9
0 0 0 0
MSC8144E Reference Manual, Rev. 3
24 23 22 21
—
W
0 0 0 0
8 7 6 5
EN8 EN7 EN6 EN5
W
0 0 0 0
24 23 22 21
—
W
0 0 0 0
8 7 6 5
DIS8 DIS7 DIS6 DIS5
W
0 0 0 0
Offset 0x204
20 19 18 17
0 0 0 0
4 3 2 1
EN4 EN3 EN2 EN1
0 0 0 0
Offset 0x20C
20 19 18 17
0 0 0 0
4 3 2 1
DIS4 DIS3 DIS2 DIS1
0 0 0 0
Freescale Semiconductor
16
0
0
EN0
0
16
0
0
DIS0
0