Pit Count Register (Pitc); Pit Register (Pitr) - Freescale Semiconductor MPC850 User Manual

Table 10-24. PISCR Field Descriptions (Continued)
Bits Name
14 PITF PIT freeze enable
0 The PIT is unaffected by the FRZ signal.
1 The FRZ signal stops the PIT.
15 PTE Periodic timer enable
0 The PIT is disabled.
1 The PIT is enabled.

10.11.2 PIT Count Register (PITC)

PITC, shown in Figure 10-30, contains a 16-bit value to be loaded into the periodic
interrupt down counter. Note that PITC is a keyed register. It must be unlocked in PITCK
before it can be written.
Bit 0 1
Field
Reset
R/W
Addr
Bit 16 17
Field
Reset
R/W
Addr
Table 10-25 describes PITC fields.
Bits Name
0–15 PITC PIT count. Contains the count for the periodic timer. Setting this field to 0xFFFF selects the
maximum count period.
16–31 — Reserved, should be cleared.

10.11.3 PIT Register (PITR)

The PIT register (PITR) is a read-only register that shows the current value in the periodic
interrupt down counter. Writes to PITR do not affect it; reads do not affect the counter.
2 3 4 5
(IMMR & 0xFFFF0000) + 0x244
18 19 20 21
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x246
Figure 10-30. PIT Count Register (PITC)
Table 10-25. PITC Field Descriptions
Chapter 10. System Interface Unit
The Periodic Interrupt Timer (PIT)
Description
6 7 8 9
PITC
—
R/W
22 23 24 25
—
R/W
Description
10 11 12 13
26 27 28 29
14 15
30 31