Periodic Interrupt Status And Control Register (Piscr) - Freescale Semiconductor MPC850 User Manual

The Periodic Interrupt Timer (PIT)
The time-out period is calculated as follows:
Solving this equation using a 32.768-KHz external clock gives:
This gives a range from 122 µs (PITC = 0x0000) to 8 seconds (PITC = 0xFFFF).
10.11.1 Periodic Interrupt Status and Control Register
(PISCR)
The periodic interrupt status and control register (PISCR), shown in Figure 10-29, contains
the interrupt request level and status bits. It also controls the 16 bits to be loaded in a
modulus counter. Note that PISCR is a keyed register. It must be unlocked in PISCRK
before it can be written.
Bit 0 1
Field
Reset
R/W
Addr
Figure 10-29. Periodic Interrupt Status and Control Register (PISCR)
Table 10-24 describes PISCR fields.
Bits Name
0–7 PIRQ Periodic interrupt request level. Configures internal interrupt levels for periodic interrupts.
Figure 10-7 shows interrupt request levels.
8 PS Periodic interrupt status. Can be cleared by writing a 1 to it (zero has no effect).
0 The PIT is unaffected.
1 The PIT has issued an interrupt.
9–12 — Reserved, should be cleared.
13 PIE Periodic interrupt enable
0 Disables the PS bit.
1 Enables the PS bit to generate an interrupt.
PITC 1
PIT = ------------------------ -
period
F
pitrtclk
PITperiod
2 3 4 5
PIRQ
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x240
Table 10-24. PISCR Field Descriptions
MPC850 Family User's Manual
+ PITC 1 +
= ----------------------------------------------------------- -
ExternalClock
 
----------------------------------------- - ÷ 4
 
o o
1 or 128
PITC 1 +
= ------------------------ -
8192
6 7 8 9 10
PS
R/W
Description
11 12 13 14
— PIE PITF PTE
15