Receive/Transmit Function Code Registers (Rfcr/Tfcr) - Freescale Semiconductor MPC850 User Manual

SPI Parameter RAM
Table 31-5. SPI Parameter RAM Memory Map (Continued)
1
Offset Name Width
0x12 — Hword
0x14 — Word
0x18 TSTATE Word
0x1C — Word
0x20 TBPTR Hword
0x22 — Hword
0x24 — Word
Note: The user must initialize only items in bold.
1
As programmed in SPI_BASE. The default value is IMMR + 0x3D80. See Section 18.6.3, "Parameter RAM."
2
Normally, these parameters need not be accessed. They are listed to help experienced users in debugging.
31.5.1 Receive/Transmit Function Code Registers
(RFCR/TFCR)
Figure 31-9 shows the fields in the receive/transmit function code registers (RFCR/TFCR)
Bit 0
Field
Reset
R/W
Addr
Figure 31-9. Receive/Transmit Function Code Registers (RFCR/TFCR)
Table 31-6 describes the RFCR/TFCR fields.
Bits Name
0–2 — Reserved, should be cleared.
BO
3–4 Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-fly, it
takes effect at the beginning of the next frame or BD. See Appendix A, "Byte Ordering."
00 Reserved
01 PowerPC little-endian.
1x Big-endian or true little-endian.
AT[1–3] Address type 1–3. Contains the user-defined function code value used during the SDMA channel
5–7
memory access. AT0 is always driven high to identify this channel access as a DMA-type access.
The Rx internal byte count
value and decremented with every byte the SDMA channels write.
Rx temp. Reserved for CPM use.
Tx internal state. Reserved for CPM use.
The Tx internal data pointer
address in the buffer to be accessed.
TxBD pointer. Points to the current Tx BD during frame transmission or the next BD to be
processed when idle. After reset or when the end of the Tx BD table is reached, the CPM
initializes TBPTR to the TBASE value. Most applications do not need to modify TBPTR,
but it can be updated when the transmitter is disabled or when no Tx buffer is in use.
The Tx internal byte count
decremented with every byte read by the SDMA channels.
Tx temp. Reserved for CPM use.
1 2
—
SPI Base + 04 (RFCR)/SPI Base + 05 (TFCR)
Table 31-6. RFCR/TFCR Field Descriptions
MPC850 Family User's Manual
Description
2
is a down-count value that is initialized with the MRBLR
2
is updated by the SDMA channels to show the next
2
is a down-count value initialized with TxBD[Data Length]and
3 4
BO
0000_0000
R/W
Description
5 6
AT[1–3]
7