NOTE:
11.9.4 TIM Channel Status and Control Registers (TSC0:TSC1)
MC68HC(7)08KH12
Rev. 1.1
—
Freescale Semiconductor
Address:
$0014
TMODH
Bit 7
6
Read:
Bit15
Bit14
Write:
Reset:
1
1
Address:
$0015
TMODL
Bit 7
6
Read:
Bit7
Bit6
Write:
Reset:
1
1
Figure 11-5. TIM Counter Modulo Registers (TMODH:TMODL)
Reset the TIM counter before writing to the TIM counter modulo registers.
Each of the TIM channel status and control registers does the following:
•
Flags input captures and output compares
•
Enables input capture and output compare interrupts
•
Selects input capture, output compare, or PWM operation
•
Selects high, low, or toggling output on output compare
•
Selects rising edge, falling edge, or any edge as the active input
capture trigger
•
Selects output toggling on TIM overflow
•
Selects 100% PWM duty cycle
•
Selects buffered or unbuffered output compare/PWM operation
5
4
3
Bit13
Bit12
Bit11
1
1
1
5
4
3
Bit5
Bit4
Bit3
1
1
1
2
1
Bit 0
Bit10
Bit9
Bit8
1
1
1
2
1
Bit 0
Bit2
Bit1
Bit0
1
1
1
Advance Information
177