The PowerPC Core
6.4.1 Control Registers
The following tables describe the core control registers, also known as special-purpose
registers, implemented within the MPC823.
Table 6-7. Standard Special-Purpose Registers
SPR
DECIMAL
SPR
5:9
1
00000
8
00000
9
00000
18
00000
19
00000
22
00000
26
00000
27
00000
272
01000
273
01000
274
01000
275
01000
287
01000
Table 6-8. Standard Timebase Register Mapping
SPR
DECIMAL
SPR
5:9
268
01000
269
01000
284
01000
285
01000
NOTES:
1.
Extended opcode for mftb, 371 rather then 339.
2.
Any write (mtspr) to this address results in an implementation-dependent software emulation interrupt.
3.
Any read (mftb) to this address results in an implementation-dependent software emulation interrupt.
Freescale Semiconductor, Inc.
REGISTER
NAME
SPR
0:4
00001
XER
01000
LR
01001
CTR
10010
DSISR
10011
DAR
10110
DEC
11010
SRR0
11011
SRR1
10000
SPRG0
10001
SPRG1
10010
SPRG2
10011
SPRG3
11111
PVR
REGISTER
NAME
SPR
0:4
01100
TBL Read
01101
TBU Read
11100
TBL Write
11101
TBU Write
MPC823 REFERENCE MANUAL
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Go to: www.freescale.com
PRIVILEGED
SERIALIZE ACCESS
No
Write:
Read:
No
No
Yes
Write:
Read:
Yes
Write:
Read:
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No (Read-Only Register)
PRIVILEGED
SERIALIZE ACCESS
2
No
2
No
3
Yes
3
Yes
Full Sync
Sync Relative to Load/
Store Operations
No
No
Full Sync
Sync Relative to Load/
Store Operations
Full Sync
Sync Relative to Load/
Store Operations
Write
Write
Write
Write
Write
Write
Write
Write - As a Store
Write - As a Store
Write - As a Store
Write - As a Store
MOTOROLA