Esai Receive Shift Registers - Freescale Semiconductor DSP56374 User Manual

23
RECEIVE HIGH BYTE
7
23
RECEIVE HIGH BYTE
SDI
7
MSB
8-BIT DATA
MSB
12-BIT DATA
MSB
MSB
MSB
(a) Receive Registers
23
TRANSMIT HIGH BYTE
7
23
TRANSMIT HIGH BYTE
7
MSB
8-BIT DATA
MSB
MSB
MSB
MSB
(b) Transmit Registers
Figure 8-14. ESAI Data Path Programming Model ([R/T]SHFD=1)
8.3.7

ESAI Receive Shift Registers

The receive shift registers (see Figure 8-13
the selected (internal/external) bit clock when the associated frame sync I/O is asserted. Data is assumed to be received MSB first if RSHFD=0
and LSB first if RSHFD=1. Data is transferred to the ESAI receive data registers after 8, 12, 16, 20, 24, or 32 serial clock cycles were counted,
depending on the slot length control bits in the RCR register.
Freescale Semiconductor
16 15
RECEIVE MIDDLE BYTE
0 7
16 15
RECEIVE MIDDLE BYTE
0 7
LSB
0 0
LSB
16-BIT DATA
20-BIT DATA
24-BIT DATA
16 15
TRANSMIT MIDDLE BYTE
0 7
16 15
TRANSMIT MIDDLE BYTE
0 7
8 BIT
LSB
0
LSB
12-BIT DATA
16-BIT DATA
20-BIT DATA
24-BIT DATA
and Figure 8-14) receive the incoming data from the serial receive data pins. Data is shifted in by
DSP56374 Users Guide, Rev. 1.2
8 7
RECEIVE LOW BYTE
0 7
8 7
RECEIVE LOW BYTE
0 7
0 0
LSB
LSB
LSB
NOTES:
1. Data is received LSB first if RSHFD=1.
2. 24-bit fractional format (ALC=0).
3. 32-bit mode is not shown.
8 7
TRANSMIT LOW BYTE
0 7
8 7
TRANSMIT LOW BYTE
0 7
20 BIT
16 BIT
12 BIT
0 0 0
LSB
LSB
LSB
NOTES:
1. Data is sent LSB first if TSHFD=1.
2. 24-bit fractional format (ALC=0).
3. 32-bit mode is not shown.
4. Data word is left aligned (TWA=0,PADC=1).
ESAI Programming Model
0
ESAI RECEIVE DATA REGISTER
(READ ONLY)
0
0
ESAI RECEIVE
SHIFT REGISTER
0
LEAST SIGNIFICANT
ZERO FILL
0
0
ESAI TRANSMIT DATA
REGISTER
0
(WRITE ONLY)
ESAI TRANSMIT
SHIFT REGISTER
0
24 BIT
SDO
TSWS4-
TSWS0
8-29