General Interrupt Enable Register 2 (Gier2_X) - Freescale Semiconductor MSC8144E Reference Manual

8.2.15 General Interrupt Enable Register 2 (GIER2_x)

GIER2_0
GIER2_1
GIER2_2
GIER2_3
Bit 31 30
— —
Type
Reset 0 0
Bit 23 22
PCI_ERR_EN DDR_ERR_EN
Type
Reset 0 0
Bit 15 14
TDM7_TERR_EN TDM7_RERR_EN TDM6_TERR_EN TDM6_RERR_EN TDM5_TERR_EN TDM5_RERR_EN TDM4_TERR_EN TDM4_RERR_EN
Type
Reset 0 0
Bit 7 6
TDM3_TERR_EN TDM3_RERR_EN TDM2_TERR_EN TDM2_RERR_EN TDM1_TERR_EN TDM1_RERR_EN TDM0_TERR_EN TDM0_RERR_EN
Type
Reset 0 0
GIER2_[0–3] include interrupt enable bits for cores 0–3 for some events that rarely occur. The
GIER2_[0–3] are reset by a hard reset event. All bits are cleared on reset. Write accesses to this
register can only be performed in supervisor mode
Name
— Reserved. Write to zero for future compatibility.
31–30
SWT4_EN SWT 4 Interrupt Enable
29
SWT3_EN SWT 3 Interrupt Enable
28
SWT2_EN SWT 2 Interrupt Enable
27
SWT1_EN SWT 1 Interrupt Enable
26
SWT0_EN SWT 0 Interrupt Enable
25
OCN_ERR_EN OCeaN Error Interrupt Enable
24
PCI_ERR_EN PCI Error Interrupt Enable
23
Freescale Semiconductor
General Interrupt Enable Register 2 for Cores 0–3
29 28
SWT4_EN SWT3_EN
0 0
21 20
DMA_ERR_EN —
0 0
13 12
0 0
5 4
0 0
Table 8-15. GIER2_x Bit Descriptions
Description
MSC8144E Reference Manual, Rev. 3
27 26
SWT2_EN SWT1_EN
R/W
0 0
19 18
CE_IECC_EN CE_DECC_EN TDM_P1ECC_EN TDM_P0ECC_EN
R/W
0 0
11 10
R/W
0 0
3 2
R/W
0 0
.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Detailed Register Descriptions
Offset 0x58
Offset 0x5C
Offset 0x60
Offset 0x64
25 24
SWT0_EN OCN_ERR_EN
0 0
17 16
0 0
9 8
0 0
1 0
0 0
Settings
Interrupt disabled
Interrupt enabled
Interrupt disabled
Interrupt enabled
Interrupt disabled
Interrupt enabled
Interrupt disabled
Interrupt enabled
Interrupt disabled
Interrupt enabled
Interrupt disabled
Interrupt enabled
Interrupt disabled
Interrupt enabled
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