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14.3.4
Port Clear Output Data Registers (PCLRR_x)
Clearing a PCLRR_x register clears the corresponding bits in the PODR_x register. Setting it has no effect.
Reading the PCLRR_x register returns 0s. The PCLRR_x registers are each eight bits wide, but not all
ports use all eight bits. The register definitions for all ports are shown in the figures below.
Address: 0xFC0A_4029 (PCLRR_UART)
0xFC0A_402E (PCLRR_LCDDATAM)
0xFC0A_402F (PCLRR_LCDDATAL)
7
R
0
W
Reset:
0
Address: 0xFC0A_4024 (PCLRR_BE)
0xFC0A_4025 (PCLRR_CS)
0xFC0A_4026 (PCLRR_FBCTL)
0xFC0A_402A (PCLRR_DSPI)
0xFC0A_402B (PCLRR_TIMER)
0xFC0A_402C (PCLRR_LCDCTL)
7
R
0
W
Reset:
0
Address: 0xFC0A_4027 (PCLRR_I2C)
0xFC0A_402D (PCLRR_LCDDATAH)
7
R
0
W
Reset:
0
Field
PCLRR_x Port x clear data bits.
0 Clears corresponding PODR_x bit
1 No effect
Note: See above figures for bit field positions.
Freescale Semiconductor
6
5
0
0
0
0
Figure 14-11. Port Clear Output Data Registers (PCLRR_x)
6
5
0
0
0
0
Figure 14-12. Port x Clear Output Data Registers (PCLRR_x)
6
5
0
0
0
0
Figure 14-13. Port x Clear Output Data Registers (PCLRR_x)
Table 14-8. PCLRR_x Field Descriptions
MCF52277 Reference Manual, Rev. 1
4
3
2
0
0
0
PCLRR_x
0
0
0
4
3
2
0
0
0
0
0
0
4
3
2
0
0
0
0
0
0
Description
General Purpose I/O Module
Access: User write-only
1
0
0
0
0
0
Access: User write-only
1
0
0
0
PCLRR_x
0
0
Access: User write-only
1
0
0
0
PCLRR_x
0
0
14-15
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