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Programming Model
8.8.10 MMU Access Protection Registers (MI_AP/MD_AP)
The IMMU access protection register (MI_AP, SPR 786) contains the settings for the
access protection groups for the IMMU. The DMMU access protection register (MD_AP,
SPR 794) is identical. Both registers are shown in Figure 8-15.
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field GP0 GP1 GP2 GP3 GP4 GP5
Reset
R/W
SPR
Figure 8-15. MMU Access Protection Registers (MI_AP/MD_AP)
MI_AP/MD_AP fields are described in Table 8-16.
Bits
Name Domain Manager Mode (Mx_CTR[GPM] = 1)
0–1
GPx
GP
00 No access
2–3
01 Client–access permission defined by page
protection bits
...
10 Reserved
11 Manager–free access
30–31
8.8.11 MMU Tablewalk Special Register (M_TW)
The MMU tablewalk special register (M_TW), shown in Figure 8-16, is a scratch register
used by tablewalk exception handlers.
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reset
R/W
SPR
Figure 8-16. MMU Tablewalk Special Register (M_TW)
8.8.12 MMU Debug Registers
The MMU CAM and RAM entries can be read through MX_CAM, MX_RAM0, and
MX_RAM1. Attempting to write to MX_CAM using an mtspr instruction loads the CAM
and RAM values of the entry indexed by DTLB_INDX to MX_CAM, MX_RAM0, and
MX_RAM1. Any register can be the source for mtspr since its value is not used. The values
of MX_CAM, MX_RAM0, and MX_RAM1 can be read using mfspr; mtspr[MX_RAM0]
and mtspr[MX_RAM1] are considered no-ops.
GP6
786 (MI_AP); 794 (MD_AP)
Table 8-16. MI_AP/MD_AP Field Descriptions
MPC850 Family User's Manual
GP7
GP8
GP9 GP10 GP11 GP12 GP13 GP14 GP15
—
R/W
PowerPC Mode (Mx_CTR[GPM] = 0)
GP = Ks/Kp as defined by PowerPC architecture
00 All accesses are treated as supervisor
01 Access permission defined by page protection
bits
10 User and supervisor interpretation is swapped
11 All accesses are treated as user
—
R/W
799
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