Slave Error Address Decode Register (Serr_Addr_Decode); Slave Error User Parity Register (Serr_User_Parity) - Texas Instruments TMS570LC4357 Technical Reference Manual

SDC MMR Registers

4.4.10 Slave Error Address Decode Register (SERR_ADDR_DECODE)

Figure 4-11. Slave Error Address Decode Register (SERR_ADDR_DECODE) (offset = 24h)
31
15
LEGEND: R = Read only; -n = value after reset
Table 4-15. Slave Error Address Decode Register (SERR_ADDR_DECODED) Field Descriptions
Bit Field
31-7 Reserved
6-0 SERR_ADDR_ DECODE

4.4.11 Slave Error User Parity Register (SERR_USER_PARITY)

Figure 4-12. Slave Error User Parity Register (SERR_USER_PARITY) (offset = 28h)
31
15
LEGEND: R = Read only; -n = value after reset
Table 4-16. Slave Error User Parity Register (SERR_USER_PARITYID) Field Descriptions
Bit Field
31-7 Reserved
6-0 SERR_USER_PARITY
278
Interconnect
Reserved
Reserved
R-0
Value Description
0 Reads return 0 and writes have no effect.
Error related to mismatch on the most-significant address bits. When set, each bit
indicates the transaction processing block inside the interconnect corresponding to
the slave that is detected by the interconnect checker to have a fault.
bit 0: L2 SRAM slave
bit 1: L2 Flash PortB slave
bit 2: L2 Flash PortA slave
bit 3: EMIF slave
bit 4: Reserved
bit 5: Cortex-R5F CPU AXI slave
bit 6: ACP-S slave
Reserved
Reserved
R-0
Value Description
0 Reads return 0 and writes have no effect.
Error related to mismatch on the parity on the response signals for the slave. When
set, each bit indicates the transaction processing block inside the interconnect
corresponding to the slave that is detected by the interconnect checker to have a
fault.
bit 0: L2 SRAM slave
bit 1: L2 Flash PortB slave
bit 2: L2 Flash PortA slave
bit 3: EMIF slave
bit 4: Reserved
bit 5: Cortex-R5F CPU AXI slave
bit 6: ACP-S slave
Copyright © 2018, Texas Instruments Incorporated
R-0
7 6
SERR_ADDR_DECODE
R-0
7 6
SERR_USER_PARITY
www.ti.com
16
0
R-0
16
0
R-0
SPNU563A – March 2018
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