Serirq Control Register 2 (Sirqcr2) - Renesas H8S/2100 Series Hardware Manual

20.3.15 SERIRQ Control Register 2 (SIRQCR2)

SIRQCR2 contains bits that enable or disable SERIRQ interrupt requests and select the host
interrupt request outputs.
Bit Bit Name Initial Value Slave Host Description
7 IEDIR3 0
6 IEDIR4 0
R/W

R/W Interrupt Enable Direct Mode 3
Selects whether an SERIRQ interrupt generation of
LPC channel 3 is affected only by a host interrupt
enable bit or by an OBF flag in addition to the enable
bit.
0: A host interrupt is generated when both the
enable bit and the corresponding OBF flag are
set
1: A host interrupt is generated when the enable bit
is set

R/W Interrupt Enable Direct Mode 4
Selects whether an SERIRQ interrupt generation of
LPC channel 4 is affected only by a host interrupt
enable bit or by an OBF flag in addition to the enable
bit.
0: A host interrupt is generated when both the
enable bit and the corresponding OBF flag are
set
1: A host interrupt is generated when the enable bit
is set
Section 20 LPC Interface (LPC)
Rev. 1.00 Apr. 28, 2008 Page 653 of 994
REJ09B0452-0100