Trigger Definition Register (Tdr) - Freescale Semiconductor MCF5329 Reference Manual

Debug Module
Field
4–3 Transfer Type. Compared with the local bus transfer type signals.
TT 00 Normal processor access
01 Reserved
10 Emulator mode access
11 Reserved
These bits also define the TT encoding for BDM memory commands. In this case, the 01 encoding indicates
an external or DMA access (for backward compatibility). These bits affect the TM bits.
2–0 Transfer Modifier. Compared with the local bus transfer modifier signals, which give supplemental information
TM for each transfer type. These bits also define the TM encoding for BDM memory commands (for backward
compatibility).
36.3.5

Trigger Definition Register (TDR)

The TDR configures the operation of the hardware breakpoint logic corresponding with the
ABHR/ABLR/AATR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers within the debug
module. TDR controls the actions taken under the defined conditions. Breakpoint logic may be configured
as a one- or two-level trigger. TDR[31–16] bits define second-level trigger, and bits 15–0 define first-level
trigger.
The debug module has no hardware interlocks to prevent spurious
breakpoint triggers while the breakpoint registers are being loaded. Disable
TDR (by clearing TDR[29,13]) before defining triggers.
A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in supervisor mode as
debug control register 0x07 using the WDEBUG instruction and through the BDM port using the
WDMREG command.
36-10
Table 36-7. AATR Field Descriptions (continued)
TT=00
TM
(normal mode)
000 Explicit cache line push
001 User data access
010 User code access
011 Reserved
100 Reserved
101 Supervisor data access
110 Supervisor code access
111 Reserved
NOTE
MCF5329 Reference Manual, Rev 3
Description
TT=10
(emulator mode)
Reserved
Reserved
Reserved
Reserved
Reserved
Emulator mode access
Emulator code access
Reserved
Freescale Semiconductor