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Triple Timer Module Programming Model
Mode 10 (internal clock): TRM = 0
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter (TCR)
TCPR
TCF (Compare Interrupt if TCIE = 1)
TOF (Overflow Interrupt if TOIE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1)
TIO can connect to the RESET pin, internal hardware preserves the TIO value and
direction for an additional 2.5 clocks to ensure a reset of valid length.
9.3.4.3
Reserved Modes
Modes 8, 11, 12, 13, 14, and 15 are reserved.
9.3.5
Special Cases
The following special cases apply during wait and stop state.
•
Timer behavior during wait — Timer clocks are active during the execution of the WAIT instruction and timer activity is
undisturbed. If a timer interrupt is generated, the DSP56374 leaves the wait state and services the interrupt.
•
Timer behavior during stop — During execution of the STOP instruction, the timer clocks are disabled, timer activity stops, and the
TIO signals are disconnected. Any external changes that happen to the TIO signals are ignored when the DSP56374 is in stop state.
To ensure correct operation, disable the timers before the DSP56374 is placed in stop state.
9.3.6
DMA Trigger
Each timer can also trigger DMA transfers if a DMA channel is programmed to be triggered by a timer event. The timer issues a DMA trigger
on every event in all modes of operation. To ensure that all DMA triggers are serviced, provide for the preceding DMA trigger to be serviced
before the DMA channel receives the next trigger.
9.4
Triple Timer Module Programming Model
The timer programmer's model in
9.4.1
Prescaler Counter
The prescaler counter is a 21-bit counter that decrements on the rising edge of the prescaler input clock. The counter is enabled when at least
one of the three timers is enabled (that is, one or more of the timer enable bits are set) and is using the prescaler output as its source (that is,
one or more of the PCE bits are set).
9-18
first event
N
0
N
M
float
low
float
high
Figure 9-19. Watchdog Toggle Mode
Figure 9-20
shows the structure of the timer registers.
DSP56374 Users Guide, Rev. 1.2
TRM = 1 is not useful for watchdog function
M
M + 1
N + 1
0
1
Freescale Semiconductor
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