Overview; Features; Modes Of Operation - Freescale Semiconductor MSC8144E Reference Manual

RapidIO Interface Dedicated DMA Controller
17.1

Overview

The dedicated DMA controller has four high-speed DMA channels. Each one of the DSP cores
can initiate DMA transfers. All channels are capable of complex data movement and advanced
transaction chaining. Operations, such as descriptor fetches and block transfers, are initiated by
each channel. A channel is selected by the arbitration logic and information is passed to the
source and destination control blocks for processing. The source and destination blocks generate
read and write requests to the address tenure engine, which manages the DMA master port
address interface. After a transaction is accepted by the master port, control is transferred to the
data tenure engine that manages the read and write data transfers. A channel remains active in the
shared resources for the duration of the data transfer unless the allotted bandwidth per channel is
reached.
17.1.1

Features

The dedicated DMA controller offers the following features:
Four high-speed/high-bandwidth channels accessible by local and remote masters
Basic DMA operation modes (direct, simple chaining)
Extended DMA operation modes (advanced chaining and stride capability)
Cascading descriptor chains
Misaligned transfers
Programmable bandwidth control between channels
Three priority levels supported for source and destination transactions
Interrupt on error and completed segment, list, or link
An Address Translation Management Unit (ATMU) with 10 local access address
windows. The ATMU translates a request address into a logical device source/destination.
17.1.2

Modes of Operation

The MPC8144E dedicated DMA controller has two modes of operation: basic and extended.
Basic mode is the DMA legacy mode. It does not support advanced features. Extended mode
supports advanced features like striding and flexible descriptor structures.
These two basic modes allow users to initiate and end DMA transfers in various ways. Table
17-1 summarizes the relationship between the modes and the following features:
Direct mode. No descriptors are involved. Software must initialize the required fields as
described in Table 17-1 before starting a transfer.
Chaining mode. Software must initialize descriptors in memory and the required fields as
described in Table 17-1 before starting a transfer.
17-2
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor