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Programmer's Model
9.7.3
SCLPC FIFO Registers—MBAR + 0x3C40
LPC uses a single FIFO that changes direction based on the Rx/Tx mode. Software controls direction change and flushes FIFO before
changing directions. FIFO memory is 512Bytes (32 x 128).
LPC FIFO is controlled by six 32-bit registers. These registers are located at an offset from MBAR of 0x3C40. Register addresses are relative
to this offset. Therefore, the actual register address is:
Hyperlinks to the LPC FIFO registers are provided below:
•
Section 9-18, LPC Rx/Tx FIFO Data Word Register
(0x3C40)
•
Section 9-19, LPC Rx/Tx FIFO Status Register
(0x3C44)
•
Section 9-20, LPC Rx/Tx FIFO Control Register
(0x3C48)
9.7.3.1
LPC Rx/Tx FIFO Data Word Register—MBAR + 0x3C40
LPC_rx/tx_fifo_data_word_register
msb 0
1
R
W
RESET:
X
X
16
17
R
W
RESET:
X
X
Note: X: Bit does not reset to a defined value.
9-28
MBAR + 0x3C40 + register address
Table 9-18. LPC Rx/Tx FIFO Data Word Register
2
3
4
5
6
X
X
X
X
X
18
19
20
21
22
X
X
X
X
X
MPC5200B Users Guide, Rev. 1
•
Section 9-21, LPC Rx/Tx FIFO Alarm Register
(0x3C4C)
•
Section 9-22, LPC Rx/Tx FIFO Read Pointer Register
(0x3C50)
•
Section 9-23, LPC Rx/Tx FIFO Write Pointer Register
(0x3C54)
7
8
9
10
FIFO_Data_Word
X
X
X
X
23
24
25
26
FIFO_Data_Word
X
X
X
X
11
12
13
14
15
X
X
X
X
27
28
29
30
31 lsb
X
X
X
X
Freescale Semiconductor
X
X
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