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Serial Host Interface Programming Model
7.4.6.11
HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12
The read/write control bits HRIE[1:0] are used to enable the SHI receive-data interrupts. If HRIE[1:0] are cleared, receive interrupts are
disabled, and the HRNE and HRFF (bits 17 and 19, see below) status bits must be polled to determine if there is data in the receive FIFO. If
HRIE[1:0] are not cleared, receive interrupts are generated according to
HRIE[1:0]
00
01
10
11
Clearing HRIE[1:0] masks a pending receive interrupt only after a one instruction cycle delay. If
HRIE[1:0] are cleared in a long interrupt service routine, it is recommended that at least one other
instruction separate the instruction that clears HRIE[1:0] and the RTI instruction at the end of the
interrupt service routine.
7.4.6.12
HCSR Host Transmit Underrun Error (HTUE)—Bit 14
The read-only status bit HTUE indicates whether a transmit-underrun error occurred. Transmit-underrun errors can occur only when operating
2
I
C
in the SPI slave mode or the
can occur. HTUE is set when both the shift register and the HTX register are empty and the external master begins reading the next word:
•
When operating in the
transmitted word.
•
When operating in the SPI mode, HTUE is set at the first clock edge if CPHA = 1; it is set at the assertion of SS if CPHA = 0.
If a transmit interrupt occurs with HTUE set, the transmit-underrun interrupt vector is generated. If a transmit interrupt occurs with HTUE
cleared, the regular transmit-data interrupt vector is generated. HTUE is cleared by reading the HCSR and then writing to the HTX register.
HTUE is cleared by hardware reset, software reset, SHI individual reset and during the stop state.
7.4.6.13
HCSR Host Transmit Data Empty (HTDE)—Bit 15
The read-only status bit HTDE indicates whether the HTX register is empty and can be written by the DSP. HTDE is set when the data word
is transferred from HTX to the shift register, except in SPI master mode when CPHA = 0 (see HCKR). When in the SPI master mode with
CPHA = 0, HTDE is set after the end of the data word transmission. HTDE is cleared when the DSP writes the HTX either with write
instructions or DMA transfers. HTDE is set by hardware reset, software reset, SHI individual reset and during the stop state.
7.4.6.14
HCSR Reserved Bits—Bits 23, 18 and 16
These bits are reserved. They read as zero and should be written with zero for future compatibility.
7.4.6.15
Host Receive FIFO Not Empty (HRNE)—Bit 17
The read-only status bit HRNE indicates that the Host Receive FIFO (HRX) contains at least one data word. HRNE is set when the FIFO is
not empty. HRNE is cleared when HRX is read by the DSP (read instructions or DMA transfers), reducing the number of words in the FIFO
to zero. HRNE is cleared during hardware reset, software reset, SHI individual reset and during the stop state.
7.4.6.16
Host Receive FIFO Full (HRFF)—Bit 19
The read-only status bit HRFF indicates, when set, that the Host Receive FIFO (HRX) is full. HRFF is cleared when HRX is read by the DSP
(read instructions or DMA transfers) and at least one place is available in the FIFO. HRFF is cleared by hardware reset, software reset, SHI
individual reset and during the stop state.
7-10
Table 7-6. HCSR Receive Interrupt Enable Bits
Interrupt
Disabled
Receive FIFO not empty
Receive Overrun Error
Reserved
Receive FIFO full
Receive Overrun Error
slave mode when HCKFR is cleared. In a master mode, transmission takes place on demand and no underrun
2
I
C
mode, HTUE is set in the falling edge of the ACK bit. In this case, the SHI retransmits the previously
DSP56374 Users Guide, Rev. 1.2
Table
7-6. HRIE[1:0] are cleared by hardware and software reset.
Not applicable
HRNE = 1 and HROE = 0
HROE = 1
Not applicable
HRFF = 1 and HROE = 0
HROE = 1
NOTE
Condition
Freescale Semiconductor
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