Idma Channel Operation; Activating An Idma Channel; Suspending An Idma Channel; Idma Interface Signals—Dreq And Sdack - Freescale Semiconductor MPC850 User Manual

IDMA Emulation

19.3.6 IDMA Channel Operation

An IDMA channel operation consists of the following events—IDMA channel
initialization, data transfer, and block termination. In the initialization phase, the core loads
the global IDMA channel information into the IDMA parameter RAM, builds the IDMA
BD table, and starts the channel. In the transfer phase, the CPM accepts a transfer request,
reads the transfer-specific information from the current BD into the IDMA parameter
RAM, programs the physical SDMA channel, and provides addressing and bus control. The
termination phase begins when the transfer byte count reaches zero (or a bus error occurs).
The CPM then interrupts the core (unless masked), and the current BD pointer moves to the
next BD in the table.
To begin a block transfer, initialize the IDMA registers, and build the IDMA BDs with
information describing the data block, device type, and other special control options. See
Section 19.3.2, "IDMA Parameter RAM," and Section 19.3.5, "IDMA CP Commands."

19.3.6.1 Activating an IDMA Channel

IDMA requests are generated externally via the DREQ signals. (There is no mechanism for
generating internal IDMA requests.) After initializing the IDMA parameter RAM and the
BD table, enable the DREQ signal by setting the corresponding PCSO[DREQ] of the
port C special options register; see Section 34.4.1.4, "Port C Special Options Register
(PCSO)." Enabling the DREQ signal effectively activates the corresponding IDMA
channel. Requests for IDMA1 have priority over IDMA2.

19.3.6.2 Suspending an IDMA Channel

Disabling the corresponding DREQ signal by clearing the corresponding PCSO[DREQ]
suspends the IDMA channel transfer. A transfer in progress will be completed before the
bus is released. No further bus cycles are started while PCSO[DREQ] remains cleared.
During channel suspension, the core can access IDMA internal registers to determine the
status of the channel or to alter parameters. If PCSO[DREQ] is set again while a transfer
request is pending, the channel arbitrates for the bus and continues normal operation.
19.3.7 IDMA Interface Signals—DREQ and SDACK
Each IDMA channel (IDMA1 and IDMA2) has two dedicated control signals—DMA
request (DREQ) and SDMA acknowledge (SDACK). DREQ0 and SDACK1 are dedicated
to IDMA1, while DREQ1 and SDACK2 are for IDMA2.
DREQ and SDACK are the handshake signals between the MPC850 and an external
peripheral requesting service. A peripheral requests IDMA service directly to the CPM by
asserting DREQ. When the CPM begins the transfer, it acknowledges the peripheral by
asserting SDACK. A requesting peripheral can either be the source or the destination of an
IDMA transfer. Note that SDACK is not used for memory/memory transfers.
The following subsections discuss the interface signals used for requesting
memory/memory and peripheral/memory transfers.
Chapter 19. SDMA Channels and IDMA Emulation