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Programmer's Model
9.7.3.3
LPC Rx/Tx FIFO Control Register—MBAR + 0x3C48
msb 0
1
R
Reserved
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:1
—
2
WFR
3:4
—
5:7
GR
8:31
—
9.7.3.4
LPC Rx/Tx FIFO Alarm Register—MBAR + 0x3C4C
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:22
—
23:31
Alarm
9-30
Table 9-20. LPC Rx/Tx FIFO Control Register
2
3
4
5
6
WFR
Reserved
GR
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Reserved
When bit sets, FIFO Controller assumes next data write is End of Frame (EOF).
Note: This module does not support Framing. This bit should remain low.
Reserved
Granularity—bits control high "watermark" point at which FIFO negates Alarm condition (i.e.,
request for data). It represents the number of free bytes times 4.
000 = FIFO waits to become completely full before stopping data request.
001 = FIFO stops data request when only one long word of space remains.
Reserved
Table 9-21. LPC Rx/Tx FIFO Alarm Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
Reserved
0
0
0
0
0
Reserved
User writes these bits to set low level "watermark", which is the point where FIFO asserts
request for BestComm Controller data filling. Value is in bytes. For example, with Alarm = 32,
alarm condition occurs when FIFO contains 32Bytes or less. Once asserted, alarm does not
negate until high level mark is reached, as specified by FIFO control register granularity bits.
MPC5200B Users Guide, Rev. 1
7
8
9
10
11
1
0
0
0
23
24
25
26
27
Reserved
0
0
0
0
Description
7
8
9
10
11
Reserved
0
0
0
0
23
24
25
26
27
Alarm
0
0
0
0
Description
12
13
14
15
Reserved
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
12
13
14
15
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
Freescale Semiconductor
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