Sdram Control Register (Sdcr) - Freescale Semiconductor MCF5329 Reference Manual

Devices supported: mcf5327; mcf5328; mcf53281; mcf5329
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Field
31–30
Bank address. Driven onto SD_BA[1:0] along with a
BK
simultaneously. SDCR[CKE] must be set before attempting to generate an
value is used to select between
00 Load mode register command (
01 Load extended mode register command (
10 Load extended mode register command (
11 Reserved
29–18
Address. Driven onto SD_A[11:0] along with an
AD
extended mode) register data.
17
Reserved, must be cleared.
16
Command. This bit is write-only and always returns a 0 when read.
CMD
1 Generate an
LMR
0 Do not generate any command
15–0
Reserved, must be cleared.
18.4.2

SDRAM Control Register (SDCR)

The SDCR
(Figure
18-6) controls SDRAMC operating modes, including refresh count and address line
muxing.
Address: 0xFC0B_8004 (SDCR)
31
30
29
R MODE
DDR_
CKE
_EN
MODE
W
Reset
0
0
0
15
14
13
R
0
0
MEM_
PS
W
Reset
0
0
0
Field
31
SDRAM mode register programming enable.
MODE_EN
0 SDMR locked, cannot be written.
1 SDMR enabled, can be written.
Note: MODE_EN must be cleared during normal operation,
30
Clock enable. CKE must be set to perform normal read and write operations. Clear CKE to put the memory in
CKE
self-refresh or power-down mode.
0 SD_CKE is negated (low)
1 SD_CKE is asserted (high)
Freescale Semiconductor
Table 18-7. SDMR Field Descriptions
and
commands.
LMR
LEMR
)
LMR
LEMR
LEMR
LMR
/
command
LEMR
28
27
26
25
0
0
REF_
ADDR_MUX
EN
0
0
0
0
12
11
10
9
0
0
DQS_OE
0
0
0
0
Figure 18-6. SDRAM Control Register (SDCR)
Table 18-8. SDCR Field Descriptions
MCF5329 Reference Manual, Rev 3
Description
/
command. All SDRAM chip selects are asserted
LMR
LEMR
/
LMR
LEMR
) for non-mobile DDR devices
) for mobile DDR devices
/
command. The AD value is stored as the mode (or
LEMR
24
23
22
21
0
OE_
RULE
0
0
0
0
8
7
6
5
0
0
0
0
0
0
0
0
Description
SDRAM Controller (SDRAMC)
command. The SD_BA[1:0]
Access: User read/write
20
19
18
17
REF_CNT
0
0
0
0
4
3
2
1
0
0
0
0
IREF IPALL
0
0
0
0
18-15
16
0
0
0
0

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