Sdram Control Register (Sdcr) - Freescale Semiconductor MCF52277 Reference Manual

Field
31–30 Bank address. Driven onto SD_BA[1:0] along with a
BK simultaneously. SDCR[CKE] must be set before attempting to generate an
value is used to select between
00 Load mode register command (
01 Load extended mode register command (
10 Load extended mode register command (
11 Reserved
29–18 Address. Driven onto SD_A[11:0] along with an
AD extended mode) register data.
17 Reserved, must be cleared.
16 Command. This bit is write-only and always returns a 0 when read.
CMD 1 Generate an
0 Do not generate any command
15–0 Reserved, must be cleared.
19.4.2

SDRAM Control Register (SDCR)

The SDCR (Figure 19-6) controls SDRAMC operating modes, including refresh count and address line
muxing.
Address: 0xFC0B_8004 (SDCR)
31 30
R MODE
DDR_
CKE
_EN MODE
W
Reset 0 0
15 14
R 0 0
MEM_
W
Reset 0 0
Field
31 SDRAM mode register programming enable.
MODE_EN 0 SDMR locked, cannot be written.
1 SDMR enabled, can be written.
Note: MODE_EN must be cleared during normal operation,
30 Clock enable. CKE must be set to perform normal read and write operations. Clear CKE to put the memory in
CKE self-refresh or power-down mode.
0 SD_CKE is negated (low)
1 SD_CKE is asserted (high)
Freescale Semiconductor
Table 19-7. SDMR Field Descriptions
and
LMR
)
LMR
/ command
LMR LEMR
29 28 27 26
0 0
REF_
EN
0 0 0 0
13 12 11 10
0
DQS_OE
PS
0 0 0 0
Figure 19-6. SDRAM Control Register (SDCR)
Table 19-8. SDCR Field Descriptions
MCF52277 Reference Manual, Rev. 1
Description
/ command. All SDRAM chip selects are asserted
LMR LEMR
commands.
LEMR
) for non-mobile DDR devices
LEMR
) for mobile DDR devices
LEMR
/ command. The AD value is stored as the mode (or
LMR LEMR
25 24 23 22
0
OE_
ADDR_MUX
RULE
0 0 0 0
9 8 7
0 0 0 0
0 0 0 0
Description
SDRAM Controller (SDRAMC)
/ command. The SD_BA[1:0]
LMR LEMR
Access: User read/write
21 20 19
REF_CNT
0 0 0
6 5 4 3
0 0 0
0 0 0
18 17 16
0 0 0
2 1 0
0 0 0
IREF IPALL
0 0 0
19-15