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LocalPlus Bus (External Bus Interface)
Bits
Name
22
AIE
23
NIE
24:30
—
31
ME
9.7.2.5
SCLPC Bytes Done Status Register—MBAR + 0x3C14
msb 0
1
R
Reserved
W
RESET:
0
0
16
17
R
W
RESET:
X
X
Note: X: Bit does not reset to a defined value.
Bits
Name
0:2
—
3
AT
4:6
—
9-26
Abort Interrupt Enable. If set, and a fifo error occurs during packet transmission, a cpu
interrupt from SCLPC will be generated. In any case, the Packet will be terminated
and an Abort Status bit will be set.
Note: This bit does *not* affect the Requestor to BestComm in any way.
Normal Interrupt Enable. This bit, if set enables a cpu interrupt to occur at the end of
a normally terminated Packet. There is also a NT status bit which sets in any case.
Note: This bit does *not* affect the Requestor to BestComm in any way.
Reserved
Master Enable. This bit must be set to 1 to allow a Restart to be generated to the
SCLPC state machine. Restart is achieved by writing 1 to Byte 0 of the Packet_Size
register. This ME bit must also be set for a Restart to occur.
Note: ME being low (inactive) will also clear Interrupt and Interrupt status. But it does
*NOT* affect the BestComm Requestor.
Table 9-17. SCLPC Bytes Done Status Register
2
3
4
5
6
AT
Reserved
rwc
0
0
0
0
0
18
19
20
21
22
X
X
X
X
X
Reserved
Abort Termination. This bit will be set to 1 if the Packet has terminated abnormally
(which is only possible if a fifoError occurred).
Note: This bit is ANDed with the AIE bit above to generate a single CPU interrupt
signal to the core. This bit is "sticky write to 1" for clearing the bit and clearing the
interrupt.
Note: This bit (and any interrupt) is also cleared if; 1) RC bit is set, 2) ME bit is clear,
or 3) Restart occurs.
Reserved
MPC5200B Users Guide, Rev. 1
Notes
Description
7
8
9
10
NT
rwc
0
X
X
X
23
24
25
26
Bytes Done
Read Only
X
X
X
X
Description
11
12
13
14
Bytes Done
Read Only
X
X
X
X
27
28
29
30
31 lsb
X
X
X
X
Freescale Semiconductor
15
X
X
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