Background/Mode Select (Bkgd/Ms) - Freescale Semiconductor MC9S08PT60 Reference Manual

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Chapter 2 Pins and connections

2.2.5 Background/mode select (BKGD/MS)

During a power-on-reset (POR) or background debug force reset, the PTA4/ACMPO/
BKGD/MS pin functions as a mode select pin. Immediately after internal reset rises the
pin functions as the background pin and can be used for background debug
communication. While the pin functions as a background/mode selection pin, it includes
an internal pullup device and a standard output driver.
The background debug communication function is enabled when SOPT1[BKGDPE] bit
is set. SOPT1[BKGDPE] is set following any reset of the MCU and must be cleared to
use the PTA4/ACMPO/BKGD/MS pin's alternative pin functions.
If this pin is floating, the MCU will enter normal operating mode at the rising edge of
reset. If a debug system is connected to the 6-pin standard background debug header, it
can hold BKGD/MS low during the POR or immediately after issuing a background
debug force reset, which will force the MCU into active background mode.
The BKGD pin is used primarily for background debug controller (BDC)
communications using a custom protocol that uses 16 clock cycles of the target MCU's
BDC clock per bit time. The target MCU's BDC clock can run as fast as the bus clock, so
there should never be any significant capacitance connected to the BKGD/MS pin that
interferes with background serial communications. When the pin performs output only
PTA4, it can drive only capacitance-limited MOSFET. Driving a bipolar transistor
directly by PTA4 is prohibited because this can cause mode entry fault and BKGD errors.
Although the BKGD pin is a pseudo open-drain pin, the background debug
communication protocol provides brief, actively driven, high speedup pulses to ensure
fast rise time. Small capacitances from cables and the absolute value of the internal
pullup device play almost no role in determining rise and fall time on the BKGD pin.
PTA5/IRQ/TCLK0/RESET
Optional Manual Reset
BKGD/MS
V
V
DD
SS
Figure 2-9. Typical debug circuit
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
Freescale Semiconductor, Inc.
49

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