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Address: 0xFC0A_C030 (LCD_DCR)
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
0 0 0 0 0 0 0 0 0 0
BURST
W
Reset
1
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Field
31
Burst length. Determines whether the burst length is fixed or dynamic.
BURST
0 Burst length is dynamic
1 Burst length is fixed
30–21
Reserved, must be cleared.
20–16
DMA high mark. Establishes the high mark for DMA requests. For dynamic burst length, after the DMA request is
HM
made, data is loaded and the pixel buffer continues to be filled until the number of empty longwords left in the DMA
FIFO is equal to the high mark minus 2. The minimum HM setting in dynamic burst is 3.
For fixed burst length, the burst length (in longwords) of each request is equal to the HM setting and its value must
be larger than TM.
15–5
Reserved, must be cleared.
4–0
DMA trigger mark. Sets the low-level mark in the pixel buffer to trigger a DMA request. The low-level mark equals
TM
the number of longwords left in the pixel buffer.
For SDRAM access, a fixed burst length of 16 is recommended:
BURST = 1; HM = 16; TM = 4
For a heavily loaded bus that requires SDRAM access, a dynamic burst length is recommended:
BURST = 0; HM = 4; TM = 8
22.3.14 LCDC Refresh Mode Control Register (LCD_RMCR)
The refresh mode control register is used to enable/disable self-refresh mode.
Address: 0xFC0A_C034 (LCD_RMCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELF_
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-16. LCD Refresh Mode Control Register (LCD_RMCR)
Freescale Semiconductor
Figure 22-15. LCD DMA Control Register (LCD_DCR)
Table 22-16. LCD_DCR Field Descriptions
NOTE
MCF5329 Reference Manual, Rev 3
Liquid Crystal Display Controller (LCDC)
0 0 0 0 0 0 0 0 0 0 0
HM
Description
8
Access: User read/write
8
7
6
5
4
3
2
1
0
TM
Access: User read/write
7
6
5
4
3
2
1
0
REF
0
22-17
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