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Clock Generator
EXTAL
Predivider
1 to 31
PD[4–0]
5.5
Clock Generator
Figure 5-8
shows the Clock Generator block diagram. The components of the Clock Generator are described in the following sections.
EXTAL
PLL OUT
5.5.1
Low-Power Divider (LPD)
The Clock Generator section consists of a divider connected to the output of the PLL. The Low-Power Divider (LPD) divides the output
frequency of the PLL by any power of 2 from 2
PLL Control Register (PCTL) Division Factor bits DF[2–0]. Since the LPD is not in the closed loop of the PLL, changes to the DF [2-0] bits
do not cause a loss of lock condition. The result is a significant power savings when the LPD operates in low-power consumption modes as
the device is not involved in intensive calculations. When the device is required to exit a low-power mode, it can immediately do so with no
time needed for clock recovery or PLL lock.
5.6
Operating Frequency (Fosc)
The output stage of the Clock Generator generates the clock signals to the core and the device peripherals. The input source to the clock
generator is selected between:
EXTAL
•
(PEN = 0, PLL disabled), which generates the device frequency from the EXTAL clock directly.
•
PLL Output (PEN = 1, PLL enabled), which generates a device frequency defined by the following formula:
5-6
Fref
Phase
Charge Pump
Detector
and
Loop Filter
Frequency
Divider
MF[7–0]
1 to 255
Figure 5-7. PLL Out = VCO Out/4 [OD1 = 1, OD0 = 1]
Figure 5-8. CLKGEN Block Diagram
0
7
to 2
. The Division Factor (DF) of the LPD can be modified by changing the value of the
Fosc
=
DSP56374 Users Guide, Rev. 1.2
OD1
VCO Out
0
VCO
1
Divide
by 2
FM
Divide
by 2
NOTE:
5 MHz < Fref < 20 MHz
300 MHz < VCO Out< 600 MHz
Low-Power
Divider
0
7
2
to 2
DF[2–0]
Fextal
--------------- -
DF
Clock
Generator
0
0
PLL Out
1
1
PEN
OD0
2-Phase
Core
Clock
(F
)
OSC
Freescale Semiconductor
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