Motorola PowerQUICC II MPC8280 Series Reference Manual page 376

Configuration Registers
9.11.2.5 Revision ID Register
Figure 9-37 and Table 9-24 describe the revision ID register.
7
Field
Reset
R/W
Addr
Table 9-24. Revision ID Register Description
Bits Name
7–0 Revision ID
9.11.2.6 PCI Bus Programming Interface Register
Figure 9-38 and Table 9-25 describe the PCI bus programming interface register.
7
Field
Reset
R/W
Addr
Figure 9-38. PCI Bus Programming Interface Register
Table 9-25. PCI Bus Programming Interface Register Description
Bits Name
7–0 Programming interface
9-54
Freescale Semiconductor, Inc.
Refer to Table 9-24.
Figure 9-37. Revision ID Register
Reset
Value
Revision Specifies a device-specific revision code for the MPC8280 (assigned
Dependent by Motorola). Revision ID = 0x11 for .25 micron revisions A.0, B.1, and
C.0
Refer to Table 9-25.
0x00 When the PCI bridge is configured as host bridge.
0x01 When the PCI bridge is configured as a peripheral device to indicate the
programming model supports the I
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RID
R
0x08
Description
PI
R
0x09
Description
O interface.
2
0
0
MOTOROLA