Motorola PowerQUICC II MPC8280 Series Reference Manual page 375

Reads to this register behave normally. Writes are slightly different in that bits can be
cleared, but not set. A bit is cleared whenever the register is written, and the data in the
corresponding bit location is set. For example, to clear bit 14 and not affect any other bits
in the register, write the value 0b0100_0000_0000_0000 to the register.
15 14 13
Field DPERR SSERR RM-A RT-A ST-A DEVSEL_T DPD FB-BC
Reset
R/W
Addr
Table 9-23 describes the PCI bus status register fields.
Table 9-23. PCI Bus Status Register Description
Bits Name
15 Detected parity error
14 Signaled system error
13 Received master-abort Set whenever the PCI bridge, acting as the PCI master on the PCI bus, terminates
12 Received target-abort
11 Signaled target-abort
10–9 DEVSEL timing
8 Data parity detected
7 Fast back-to-back
capable
6 —
5 66-MHz capable
4 Capabilities List
3–0 —
MOTOROLA
Freescale Semiconductor, Inc.
12 11 10 9 8
0000_0000_1011_0000
R/W
Figure 9-36. PCI Bus Status Register
Set whenever the PCI bridge detects a parity error on the PCI bus, even if parity
error handling is disabled (as controlled by bit 6 in the PCI bus command register).
Set whenever the PCI bridge asserts SERR on the PCI bus.
a transaction (except for a special-cycle) using master-abort.
Set whenever a PCI bridge-initiated transaction on the PCI bus is terminated by
a target-abort.
Set whenever the PCI bridge, acting as the PCI target on the PCI bus, issues a
target-abort to a PCI master.
Hardwired to 0b00, indicating that the PCI bridge uses fast device-select timing
on the PCI bus.
Set upon detecting a data parity error on the PCI bus. Three conditions must be
met for this bit to be set:
• The PCI bridge detects a parity error.
• The PCI bridge is acting as the bus master for the operation in which the error
occurred.
• Bit 6 in the PCI bus command register is set.
Hardwired to 1, indicating that the PCI bridge as a target is capable of accepting
fast back-to-back transactions.
Reserved, should be cleared.
This bit is read-only and indicates that the PCI bridge is capable of 66-MHz PCI
bus operation on the PCI bus.
Hardwired to 1, indicating that the PCI bridge implements new capabilities on the
PCI bus.
Reserved, should be cleared.
Chapter 9. PCI Bridge
For More Information On This Product,
Go to: www.freescale.com
7 6 5 4
— 66MHzC CL
R
0x06
Description
Configuration Registers
3 0
—
R/W
9-53