Motorola PowerQUICC II MPC8280 Series Reference Manual page 377

9.11.2.7 Subclass Code Register
Figure 9-39 and Table 9-26 describe the subclass code register.
7
Field
Reset
R/W
Addr
Table 9-26. Subclass Code Register Description
Bits Name
7–0 Subclass code
9.11.2.8 PCI Bus Base Class Code Register
Figure 9-40 and Table 9-27 describe the PCI bus class code register.
7
Field
Reset
R/W
Addr
Figure 9-40. PCI Bus Base Class Code Register
Table 9-27. PCI Bus Base Class Code Register Description
Bits Name
7–0 Base class code
When configured as a PCI agent device, the value of the
Interface, Subclass Code, and Base Class Code Registers are
0x01, 0x00, and 0x0E respectively, indicating that the
MPC8280 supports the I
the I O support is not fully standard compliant.
2
MOTOROLA
Freescale Semiconductor, Inc.
Figure 9-39. Subclass Code Register
Identifies more specifically the function of the PCI bridge (0x00 = host bridge)
Refer to Table 9-27.
0x06 When the PCI bridge is configured as a host bridge to indicate "Host Bridge".
0x0E When the PCI bridge is configured as a target device to indicate the device
is an agent and is I
NOTE: I O Compliancy
2
O protocol. The user should note that
2
Chapter 9. PCI Bridge
For More Information On This Product,
Go to: www.freescale.com
SC
0000_0000
R
0x0A
Description
BCC
R
0x0B
Description
O capable.
2
Configuration Registers
0
0
9-55