Motorola PowerQUICC II MPC8280 Series Reference Manual page 364

Configuration Registers
9.11.1.11 Error Control Register (ECR)
The error control register (ECR) register, shown in Figure 9-25, determines whether the
IOU asserts an interrupt or a machine check for the error conditions listed in Table 9-10.
The IOU asserts an interrupt or machine check only if the mask bit for the error condition
(refer to Table 9-11) is set. Each bit is defined as follows:
• Zero: The IOU issues an interrupt upon the error condition.
• One: The IOU issues a machine check upon the error condition.
31
Field
Reset
R/W
Addr
15 13
Field —
Reset
R/W
Addr
Table 9-12 describes ECR fields.
Bits Name
31–13 —
12 I2O_DBMC
11 NMI
10 IRA
9 I2O_IPQO
8 I2O_OFQO
7 PCI_PERR_WR
6 PCI_PERR_RD
5 PCI_SERR
4 PCI_TAR_ABT
3 PCI_NO_RSP
9-42
Freescale Semiconductor, Inc.
0000_0000_0000_0000
12 11 10 9
I2O_ I2O_
NMI IRA
DBMC IPQO
0000_0000_1111_1111
Figure 9-25. Error Control Register (ECR)
Table 9-12. ECR Field Descriptions
Reserved, should be cleared
I O doorbell machine check
2
0 ESR[I2O_DBMC] causes an interrupt.
1 ESR[I2O_DBMC] (if enabled) causes a machine check.
General error/interrupt indication
Illegal register access with incorrect size
I2O inbound post queue overflow
I2O outbound free queue overflow
PCI parity error received on a write
PCI parity error received on a read
PCI SERR received
PCI target abort
PCI no response (no DEVSEL; master abort)
MPC8280 PowerQUICC II Family Reference Manual
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—
R/W
0x1088E
8 7 6 5
I2O_ PERR_ PERR_ TAR_
SERR
OFQO WR RD
R/W
0x1088C
Description
4 3 2 1
DATA_ DATA_
NO_ ADDR_
PAR_ PAR_
ABT RSP PAR
RD WR
MOTOROLA
16
0