Motorola PowerQUICC II MPC8280 Series Reference Manual page 352

Configuration Registers
9.10.3 SIU Registers
PCI utilizes fields in general SIU registers (SIUMCR, TESCR1, TESCR2, and
L-TESCR1). There are also two pairs of PCI-specific registers that detect accesses from the
60x bus side to the PCI bridge (other than PCI internal registers accesses). Refer to
Section 4.3.4, "PCI Control Registers."
9.11 Configuration Registers
There are two types of configuration registers in the PCI bridge: PCI-specified and
memory-mapped. The PCI-specified type, referred to as PCI configuration registers, are
accessed through PCI configuration cycles (refer to Section 9.11.2, "PCI Bridge
Configuration Registers"). The memory-mapped configuration registers are placed in the
internal memory map of the MPC8280 and are accessed like other internal registers (refer
to Section 9.11.1, "Memory-Mapped Configuration Registers").
Both the PCI configuration and memory-mapped internal registers of the PCI bridge are
intrinsically little-endian and are described using classic bit-numbering; that is, the lowest
memory address contains the least significant byte of the register and bit 0 is the
least-significant bit of the register.
NOTE: Accessing Configuration Registers
For a PCI device to share little-endian (LE) data with the 603e
core CPU, software must byte-swap the data of the
configuration register. Refer to Section , "Accesses to
CFG_DATA without a valid offset in CFG_ADDR generates
an I/O transaction on the PCI bus.," and Section 9.11.2.27.1,
"Additional Information on Endianess."
Also note that reserved bits in the configuration registers are not guaranteed to have
predictable values. Software must preserve the values of reserved bits when writing to a
configuration register. Also, when reading from a configuration register, software should
not rely on the value of reserved bits remaining constant.
NOTE: Accessing PCI Registers in Non-PCI Mode
In non-PCI mode, a 60x bus master should not attempt to
access the PCI memory mapped configuration registers. Doing
so will cause the internal memory space of the MPC8280 to be
inaccessible. Any following access to the internal memory
space will not be terminated normally, and can only be
terminated by TEA if the 60x bus monitor is activated. The
system can recover only after a soft reset.
9-30
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MPC8280 PowerQUICC II Family Reference Manual
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