Motorola PowerQUICC II MPC8280 Series Reference Manual page 330

PCI Interface
Table 9-2. PCI Command Definitions (continued)
PCI_C/BE[3-0] Command Type
0b0111 Memory write
0b100x —
0b1010 Configuration read
0b1011 Configuration write
0b1100 Memory read multiple
0b1101 Dual address cycle
0b1110 Memory read line
0b1111 Memory write and
invalidate
9.9.1.2 PCI Protocol Fundamentals
The bus transfer mechanism on the PCI bus is called a burst. A burst is comprised of an
address phase and one or more data phases.
All signals are sampled on the rising edge of the PCI clock. Each signal has a setup and hold
window with respect to the rising clock edge, in which transitions are not allowed. Outside
this aperture, signal values or transitions have no significance.
9.9.1.2.1 Basic Transfer Control
PCI data transfers are controlled with three fundamental signals:
• FRAME is driven by an initiator to indicate the beginning and end of a transaction.
• IRDY (initiator ready) is driven by an initiator, allowing it to force wait cycles.
• TRDY (target ready) is driven by a target, allowing it to force wait cycles.
The bus is idle when both FRAME and IRDY are negated. The first clock cycle in which
FRAME is asserted indicates the beginning of the address phase. The address and the bus
command code are transferred in that cycle. The next cycle ends the address phase and
begins the data phase.
9-8
Freescale Semiconductor, Inc.
Supported as:
Initiator Target
YES YES
— —
YES YES
YES YES
YES YES
NO NO
YES YES
NO YES
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
Definition
Accesses agents mapped in memory address space.
Reserved. No response occurs.
Accesses the configuration space of each agent. An
agent is selected when its IDSEL signal is asserted. See
Section 9.9.1.4.4, "Host Mode Configuration Access" for
more detail of configuration accesses. As a target, a
configuration read is only accepted if the PCI bridge is
configured to be in agent mode.
Accesses the configuration space of each agent. An
agent is selected when its IDSEL signal is asserted. See
Section 9.9.1.4.4, "Host Mode Configuration Access". As
a target, a configuration write is only accepted if the PCI
bridge is configured to be in agent mode.
Causes a prefetch of the next cache line.
Transfers an 8 byte address to devices.
Indicates that the initiator intends to transfer an entire
cache line of data.
Indicates that the initiator will transfer an entire cache line
of data, and if PCI has any cacheable memory, this line
needs to be invalidated.
MOTOROLA