Motorola PowerQUICC II MPC8280 Series Reference Manual page 347

PCI mastered
transaction
Hit
Inbound ATU
?
Figure 9-12. Address Decode Flow Chart for PCI Mastered Transactions
When a transaction is performed by a PCI master, the bridge
checks the address against inbound ATUs and if it does not hit,
it then checks against PIMMR; if it is a hit, the bridge translates
it to a 60x cycle. Because PIMMR does not have an associated
translation register and window size definition, the translation
is performed as follows: a 128-Kbyte window is provided for
the PCI master to access the MPC8280's internal (dual port)
registers. It translates to the MPC8280's IMMR value for the
upper bits of the address. This allows the PCI master to access
any of the PCI-bridge registers without wasting an inbound
translation window. In effect, there are a total of three inbound
windows, 2 with ATUs and 1 with PIMMR.
MOTOROLA
Freescale Semiconductor, Inc.
No
PIMMR
Yes
Translate the
address
Hit
No
IMMR
?
Yes
Hit PCI
No
internal registers
?
(1)
(1): IMMR+0x10400 ≤ addr ≤ IMMR+0x10bff
Yes
Execute register
access to
PCI interface
internal registers
NOTE
Chapter 9. PCI Bridge
For More Information On This Product,
Go to: www.freescale.com
Hit
No
?
Yes
No DEVSEL
Issue transaction
to 60x bus
Address Map
9-25