Motorola PowerQUICC II MPC8280 Series Reference Manual page 340

PCI Interface
When the MPC8280 is configured as a host device, it sometimes needs to perform
configuration reads from unpopulated PCI slots (as part of the system configuration). To
avoid getting a machine check interrupt, the following steps should be taken:
1. Mask the "PCI No response" bit in the error mask register (clear bit 3). Refer to
Section 9.11.1.9, "Error Status Register (ESR)."
2. Make the PCI configuration reads.
3. Clear bit 3 in the error status register (by writing 0x08).
4. Unmask (write'1') bit 3 in the error mask register. Refer to Section 9.11.1.10, "Error
Mask Register (EMR)."
9.9.1.4.5 Agent Mode Configuration Access
When the PCI bridge is configured as an agent device, it responds to remote host generated
PCI configuration accesses to the PCI interface. This is indicated by decoding the
configuration command along with the PCI bridge's IDSEL being asserted. A remote host
can access the 256-byte PCI configuration area (Figure 9-32) and the memory-mapped
configuration registers within the PCI bridge.
9.9.1.4.6 Special Cycle Command
A special cycle command contains no explicit destination address but is broadcast to all PCI
agents. Each receiving agent must determine whether the message is applicable to itself. No
assertion of DEVSEL in response to a special cycle command is necessary.
A special cycle command is like any other bus command in that it has an address phase and
a data phase. The address phase starts like all other commands with the assertion of
FRAME and completes when FRAME and IRDY are negated. Special cycles terminate
with a master-abort. (In the special cycle case, the received-master-abort bit in the
configuration status register is not set.)
The address phase contains no valid information other than the command field. Even
though there is no explicit address, the address/data lines are driven to a stable state and
parity is generated. During the data phase, the address/data lines contain the message type
and an optional data field. The message is encoded on the sixteen least-significant bits
(AD[15-0]). The data field is encoded on AD[31-16]. When running a special cycle, the
PCI bridge can insert wait states, but because no specific target is addressed, the message
and data are valid on the first clock IRDY is asserted.
When the CONFIG_ADDRESS register gets written with a value such that the bus number
matches the bridge's bus, the device number is all ones, the function number is all ones and
the register number is zero, the next time the CONFIG_DATA register is accessed the PCI
bridge does either a special cycle or an interrupt acknowledge command. When the
CONFIG_DATA register is written, the PCI bridge generates a special cycle encoding on
9-18
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MPC8280 PowerQUICC II Family Reference Manual
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