Motorola PowerQUICC II MPC8280 Series Reference Manual page 356

Configuration Registers
31
Field
Reset
R/W
Addr
15
Field
Reset
R/W
Addr
Figure 9-17. PCI Outbound Translation Address Registers (POTARx)
Table 9-4 describes POTARx.
Bits Name
31–20 —
19–0 Translation Address
9.11.1.4 PCI Outbound Base Address Registers (POBARx)
The PCI outbound base address registers (POBARx), shown in Figure 9-18, select the base
address for the windows which are translated to the PCI address space for transactions
generated by the 60x bus master or other local devices such as the DMA controller.
31
Field
Reset
R/W
Addr
15
Field
Reset
R/W
Addr
Figure 9-18. PCI Outbound Base Address Registers (POBARx)
9-34
Freescale Semiconductor, Inc.
—
0000_0000_0000_0000
0x10802 (POTAR0); 0x1081A (POTAR1); 0x10832 (POTAR2)
0000_0000_0000_0000
0x10800 (POTAR0); 0x10818 (POTAR1); 0x10830 (POTAR2)
Table 9-4. POTARx Field Descriptions
Reserved, should be cleared.
PCI address which indicates the starting point of the outbound translated
address. The translation address must be aligned based on the window's size.
This corresponds to bits 31-12 of a 32-bit address
—
0000_0000_0000_0000
0x1080A (POBAR0); 0x10822 (POBAR1); 0x1083A (POBAR2)
0000_0000_0000_0000
0x10808 (POBAR0); 0x10820 (POBAR1); 0x10838 (POBAR2)
MPC8280 PowerQUICC II Family Reference Manual
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20
R/W
TA
R/W
Description
20
R/W
BA
R/W
19 16
TA
0
19 16
BA
0
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