Motorola PowerQUICC II MPC8280 Series Reference Manual page 334

PCI Interface
A write transaction starts when FRAME is asserted for the first time and the
PCI_C/BE[3-0] signals indicate a write command. Figure 9-5 shows an example of a single
beat write transaction.
PCI_CLK
AD[31:0]
PCI_C/BE[3:0]
FRAME
IRDY
DEVSEL
TRDY
Figure 9-6 shows an example of a burst write transaction.
PCI_CLK
AD[31:0]
PCI_C/BE[3:0]
FRAME
IRDY
DEVSEL
TRDY
A write transaction is similar to a read transaction except no turnaround cycle is needed
following the address phase because the initiator provides both address and data. Data
phases are the same for both read and write transactions.
9.9.1.3.2 Transaction Termination
The termination of a PCI transaction is orderly and systematic, regardless of the cause of
the termination. All transactions end when FRAME and IRDY are both negated, indicating
the idle cycle.
9-12
Freescale Semiconductor, Inc.
ADDR
CMD BYTE ENABLES
Figure 9-5. Single Beat Write Example
ADDR DATA1
CMD BEs 1
Figure 9-6. Burst Write Example
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DATA
DATA2 DATA3 DATA4
BEs 2 BEs 3 BEs 4
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