Motorola PowerQUICC II MPC8280 Series Reference Manual page 359

Table 9-7. PTCR Field Descriptions (continued)
Bits Name
30–24 —
23–0 Preload timer value
9.11.1.7 General Purpose Control Register (GPCR)
The general purpose control register (GPCR), shown in Figure 9-21, contains control bits
for rerouting interrupts and adjusting the DMA controller's 60x bandwidth.
31
Field
Reset
R/W
Addr
15 14
Field — INTPCI MCP2PCI
Reset
R/W
Addr
Figure 9-21. General Purpose Control Register (GPCR)
MOTOROLA
Freescale Semiconductor, Inc.
Reserved
Preload value for 24-bit discard timer. Delayed PCI read transactions to a
non-prefetchable address space remain valid within the PCI bridge a minimum of
24
(2 - Preload Timer Value) internal clock cycles. The discard timer is used to
discard delayed reads from non-prefetchable address space if the master has not
repeated the transaction in n internal clock cycles, where n = (2
Value). Valid Preload Timer Values are in the range 0x000000–0xFFFFFE.
Example: To discard a delayed completion if the PCI master has not repeated the
15
transaction in 2 PCI clocks and the internal frequency is 2 to 1 to the PCI bus. The
Preload Timer Value should equal 2
—
0000_0000_0000_0000
13 12
0000_0000_0000_0000
Chapter 9. PCI Bridge
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Go to: www.freescale.com
Description
24 16
- 2 (0xFF0000).
20
R/W
0x1087E
—
R/W
0x1087C
Configuration Registers
24
- Preload Timer
19 18 17 16
DMABC —
1 0
LE_MODE
9-37