Motorola PowerQUICC II MPC8280 Series Reference Manual page 346

Address Map
60x bus mastered
transaction
Hit
IMMR
?
Yes
Hit PCI
internal registers
?
(1)
Yes
Execute register
access to
PCI interface
internal registers
(1): IMMR+0x10400 ≤ addr ≤ IMMR+0x10bff
Figure 9-11. Address Decode Flow Chart for 60x Bus Mastered Transactions
Transactions directed to the MPC8280 from a PCI bus master are handled as follows:
• If the transaction address is within the internal register space of the MPC8280, the
transaction is either handled by the PCI bridge internal register logic or forwarded
to the core side of the PCI bridge to be handled by the MPC8280 internal register
logic as appropriate.
• If the transaction address is within one of the two inbound PCI translation windows,
the transaction is sent to the core side of the PCI bridge with address translation.
This window is provided for the PCI master to access the
MPC8280's internal (dual port) registers/area. Its size is
assumed to be fixed at 128K bytes. It translates to the
MPC8280's IMMR value for the upper bits of the address. This
way, the PCI master can access any of the PCI bridge registers
(DMA/MU, etc.) without wasting an inbound translation
window. In effect, it suggests that we have a total of three
inbound windows, 2 with ATUs and one with PIMMR.
An address decode flow chart for transactions from a PCI bus master to the PCI bridge is
shown in Figure 9-12.
9-24
Freescale Semiconductor, Inc.
Hit
No
PCIBR0/PCIBR1
?
No
No
No action
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
Yes
Hit
No
Outbound ATU
?
Yes
Translate the
address
Issue transaction
with translated
address to PCI
Issue transaction
with un-translated
address to PCI
MOTOROLA