Motorola PowerQUICC II MPC8280 Series Reference Manual page 358

Configuration Registers
Table 9-6. POCMRx Field Descriptions (continued)
Bits Name
28–20 —
19–0 Comparison mask
9.11.1.6 Discard Timer Control Register (PTCR)
The discard timer control register (PTCR), shown in Figure 9-20, configures the discard
timer used to put a time limit on delayed read transactions from non-prefetchable memory.
31 30
Field EN
Reset
R/W
Addr
15
Field
Reset
R/W
Addr
Figure 9-20. Discard Timer Control register (PTCR)
Table 9-7 describes PTCR fields.
Bits Name
31 Enable
9-36
Freescale Semiconductor, Inc.
Reserved, should be cleared.
Comparison mask indicates the size of the space to be translated. The value in the
register represents which of the most significant address bits to compare for a
window match. Non-contiguous comparison masks will exhibit unpredictable
behavior.
Examples:
POCMR = 0b0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
Translation is disabled. All addresses received pass through unaltered.
POCMR = 0b1xxx_xxxx_xxxx_1111_1111_1111_1111_1111
20 bits (physical address bits 31-12) are comparison masked for a 4Kbyte window
size. This is the smallest window size allowed.
POCMR = 0b1xxx_xxxx_xxxx_1111_1111_1111_0000_0000
12 bits (physical address bits 31-20) for a 1Mbyte window size.
—
0000_0000_0000_0000
0000_0000_0000_0000
Table 9-7. PTCR Field Descriptions
Discard timer enable.
0 Disable the discard timer
1 Enable the discard timer
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Description
24 23
R/W
0x1087A
PTV
R/W
0x10878
Description
16
PTV
0
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