Motorola PowerQUICC II MPC8280 Series Reference Manual page 362

Configuration Registers
Table 9-10 describes ESR fields.
Bits Name
31–13 —
12 I2O_DBMC
11 NMI
10 IRA
9 I2O_IPQO
8 I2O_OFQO
7 PCI_PERR_WR
6 PCI_PERR_RD
5 PCI_SERR
4 PCI_TAR_ABT
3 PCI_NO_RSP
2 PCI_DATA_PAR_RD
1 PCI_DATA_PAR_WR
0 PCI_ADDR_PAR
9.11.1.10 Error Mask Register (EMR)
The error mask register (EMR) register, shown in Figure 9-24, enables the IOU to assert an
interrupt or a machine check for the various types of error conditions listed in Table 9-10.
Each mask bit is active high. That is, if a bit value is zero, an interrupt or machine check is
not asserted for the corresponding error condition.
9-40
Freescale Semiconductor, Inc.
Table 9-10. ESR Field Descriptions
Reserved, should be cleared.
I O DoorBell Machine Check. When a PCI-mastered write sets IDBR[31], a
2
machine check is sent to the local processor and the event is reported in
ESR[I2O_DBMC].
This bit is also set in the following cases:
• An overflow condition in the inbound posted I
• An overflow condition in the outbound free I
These two interrupts can be masked in the I
General error/interrupt indication. In host mode, this bit is set when a 60x bus
write transaction initiated by the PCI bridge is terminated by the assertion of TEA.
In agent mode, this bit is set when the GPCR[MCP2PCI] bit is set and an internal
machine check interrupt (MCP) is issued by one of the MPC8280's MCP
sources.
Machine check and interrupt assertion is determined by ECR[11].
The reset value of ECR[11], logic zero, indicates that an interrupt will be asserted
if ESR[NMI] is set (and enabled per EMR[11]).
Illegal register access with incorrect size.
I2O inbound post queue overflow.
I2O outbound free queue overflow.
PCI parity error received on a write.
PCI parity error received on a read.
PCI SERR received.
PCI target abort
PCI no response (no DEVSEL; master abort).
PCI read data parity error.
PCI write data parity error.
PCI address parity error (read or write).
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Description
O queue
2
O queue.
2
O unit.
2
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