Motorola PowerQUICC II MPC8280 Series Reference Manual page 326

Interrupts from PCI Bridge
or any other needed data will reside on the 60x bus or on the PCI bus. Because the PCI is
replacing the local bus interface when PCI_MODE is active, the PCI path is automatically
chosen whenever the choice between 60x and local bus was programmed to local. When
the PCI bridge is disabled (PCI_MODE is negated), the SDMA transfers data to local
memory through the local bus interface whenever the choice is programmed to local. No
change occurs when the programmed option is the 60x bus. Refer to the descriptions of
DTB and BIB in Table 31-16.
Although the user can direct the SDMA to the 60x bus,
transactions can be redirected to the PCI bridge if they fall in
one of the PCI windows of the 60x bus memory map (PCIBR0
or PCIBR1; refer to Section 4.3.4.1, "PCI Base Register
(PCIBRx)"). Data flow of this kind is not recommended
because it is not optimal. However, if it is implemented, the
user must set strict 60x bus mode (BCR[ETM] = 0).
9.5 Interrupts from PCI Bridge
Each of the PCI bridge interrupt sources—the PCI error condition detector, the DMA unit,
and the message unit—can generate an interrupt to the SIU interrupt controller. PCI bridge
interrupts are reflected in SIPNR_H[PCI] (refer to Section 4.3.1.4, "SIU Interrupt Pending
Registers (SIPNR_H and SIPNR_L)"). PCI bridge interrupts can be masked in general with
SIMR_H[PCI] (refer to Section 4.3.1.5, "SIU Interrupt Mask Registers (SIMR_H and
SIMR_L)"). Specific interrupt sources can be masked independently by masking the
relevant bits in the following registers—error mask register, DMA mode register, inbound
message interrupt mask register, and the outbound message interrupt mask register. Each of
these registers is described in Section 9.11.1, "Memory-Mapped Configuration Registers."
The interrupt service routine can determine the source of the interrupt by reading the status
bits of the following registers—the error status register, the DMA general status register,
the inbound message interrupt status register, and the outbound message interrupt status
register.
For PCI interrupt vector calculation, refer to Section 4.2.4, "Interrupt Vector Generation
and Calculation."
For the priority of PCI interrupts, refer to Section 4.3.1.2, "SIU Interrupt Priority Register
(SIPRR)."
9.6 60x Bus Arbitration Priority
To prevent 60x bus arbitration deadlock, the PCI bridge should be programmed to have a
high arbitration priority level within the 60x bus. The 60x bus arbitration-level register
(PPC_ALRH) should be programmed so that the PCI request level index (0b0011) has a
9-4
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