Uart Module Initialization Sequence - Freescale Semiconductor MCF52277 Reference Manual

UART Modules
Register
UISRn
UISRn
30.5.2

UART Module Initialization Sequence

The following shows the UART module initialization sequence.
1. UCRn:
a) Reset the receiver and transmitter.
b) Reset the mode pointer (MISC[2–0] = 0b001).
2. UIMRn: Enable the desired interrupt sources.
3. UACRn: Initialize the input enable control (IEC bit).
4. UCSRn: Select the receiver and transmitter clock. Use timer as source if required.
5. UMR1n:
a) If preferred, program operation of receiver ready-to-send (RXRTS bit).
a) Select receiver-ready or FIFO-full notification (RXRDY/FFULL bit).
b) Select character or block error mode (ERR bit).
c) Select parity mode and type (PM and PT bits).
d) Select number of bits per character (B/Cx bits).
6. UMR2n:
a) Select the mode of operation (CM bits).
b) If preferred, program operation of transmitter ready-to-send (TXRTS).
c) If preferred, program operation of clear-to-send (TXCTS bit).
d) Select stop-bit length (SB bits).
7. UCRn: Enable transmitter and/or receiver.
30-28
Table 30-14. UART DMA Requests
Bit
1 Receive DMA request
0 Transmit DMA request
MCF52277 Reference Manual, Rev. 1
DMA Request
Freescale Semiconductor